STMicroelectronics STM32WLEx Reference Manual page 1112

Low-power universal asynchronous receiver transmitter (LPUART)
Character reception
During an LPUART reception, data are shifted in least significant bit first (default
configuration) through the RX pin. In this mode, the LPUART_RDR register consists of a
buffer (RDR) between the internal bus and the received shift register.
Character reception procedure
To receive a character, follow the sequence below:
1. Program the M bits in LPUART_CR1 to define the word length.
2. Select the desired baud rate using the baud rate register LPUART_BRR
3. Program the number of stop bits in LPUART_CR2.
4. Enable the LPUART by writing the UE bit in LPUART_CR1 register to '1'.
5. Select DMA enable (DMAR) in LPUART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in
multiprocessor
6. Set the RE bit LPUART_CR1. This enables the receiver which begins searching for a
start bit.
When a character is received
•
When FIFO mode is disabled, the RXNE bit is set. It indicates that the content of the
shift register is transferred to the RDR. In other words, data has been received and can
be read (as well as its associated error flags).
•
When FIFO mode is enabled, the RXFNE bit is set indicating that the RXFIFO is not
empty. Reading the LPUART_RDR returns the oldest data entered in the RXFIFO.
When a data is received, it is stored in the RXFIFO, together with the corresponding
error bits.
•
An interrupt is generated if the RXNEIE (RXFNEIE in case of FIFO mode) bit is set.
•
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
•
In multibuffer communication mode:
–
–
•
In single buffer mode:
–
–
1112/1306
communication.
When FIFO mode is disabled, the RXNE flag is set after every byte received and
is cleared by the DMA read of the Receive Data Register.
When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not
empty. After every DMA request, a data is retrieved from the RXFIFO. DMA
request is triggered by RXFIFO is not empty i.e. there is a data in the RXFIFO to
be read.
When FIFO mode is disabled, clearing the RXNE flag is done by performing a
software read from the LPUART_RDR register. The RXNE flag can also be
cleared by writing 1 to the RXFRQ in the LPUART_RQR register. The RXNE bit
must be cleared before the end of the reception of the next character to avoid an
overrun error.
When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not
empty. After every read operation from the LPUART_RDR register, a data is
retrieved from the RXFIFO. When the RXFIFO is empty, the RXFNE flag is
cleared. The RXFNE flag can also be cleared by writing 1 to the RXFRQ bit in the
LPUART_RQR register. When the RXFIFO is full, the first entry in the RXFIFO
must be read before the end of the reception of the next character to avoid an
overrun error. The RXFNE flag generates an interrupt if the RXFNEIE bit is set.
RM0461 Rev 5
Section 33.5.10: USART
RM0461