Output Compare Mode - Renesas M16C FAMILY Hardware Manual

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group

12.4.2 Output Compare Mode

In this mode, an interrupt request is generated when the value of TC register matches the value of
TM0 or TM1 register. Table 12.14 shows specifications in output compare mode. Figure 12.34 shows
an operation example of output compare mode.
Table 12.14 Output Compare Mode Specifications
Item
Count source
Count operation
Count start condition
Counter stop condition
Waveform output start
condition
Waveform output stop
condition
Interrupt request
generation timing
______
INT3/TC pin function
IN
P1 to P1 pins and P3
0 2
P3 pins function
2
Counter value reset timing
1
Read from timer
Write to timer
Select function
Notes:
1. TC, TM0, and TM1 registers should be accessed in 16-bit units.
2. These pins function as the CMP output pin only when the P1_i bit in the P1 register and the P3_i bit in the P3 register
are set to "1" (high). (i=0 to 2)
Rev.0.91 2003 Sep 08
f , f , f , f -fast
1 8 32 RING
• Count up
• Value in TC register is set to "0000
TCC00 bit in TCC0 register is set to "1" (count start)
TCC00 bit in TCC0 register is set to "0" (count stop)
When "1" (CMP output enabled) is written to TCOUT0 to TCOUT5 bits.
When "0" (CMP output disabled) is written to TCOUT0 to TCOUT5 bits.
• When a match occurs in compare circuit 0 [compare 0 interrupt]
• When a match occurs in compare circuit 1 [compare 1 interrupt]
• When Time C overflows [Timer C interrupt]
I/O port
to I/O port or CMP output
0
When TCC00 bit in TCC0 register is set to "0" (count stop)
• Value in compare register can be read out by reading TM0 register and TM1 register.
• Count value can be read out by reading TC register.
• Write to TC register is disabled.
• Values written to TM0 register and TM1 register are stored in compare register at the
following timings:
- When TM0 and TM1 registers are written if TCC00 bit is "0" (count stop)
- When counter overflows if TCC00 bit is "1" (in counting) and TCC12 bit in TCC1
register is "0" (free-run)
- When compare 1 matches counter if TCC00 bit is "1" and TCC12 bit is "1" (set TC
register to "0000
16
• Timer C counter reload select function
Counter value in TC register at match occurrence in compare circuit 1 is set or not set
to "0000 " selected by TCC12 bit in TCC1 register.
16
• Output level at match occurrence in compare circuit 0 can be selected by TCC15 to
TCC14 bits in TCC1 register. Similarly, output level at match occurrence in compare
circuit 1 can be selected by TCC17 to TCC16 bits in TCC1 register.
• Whether output is reversed or not can be selected by TCOUT1 to TCOUT0 bits in
TCOUT register.
page 107 of 184
Specification
" when a counting stops
16
2
" at compare 1 match)
12.4 Timer (Timer C)
2