ST STM32F423 Reference Manual page 1306

Debug support (DBG)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 DBG_CAN2_STOP: Debug CAN2 stopped when core is halted
0: Same behavior as in normal mode
1: The CAN2 received registers are frozen
Bit 25 DBG_CAN1_STOP: Debug CAN1 stopped when core is halted
0: Same behavior as in normal mode
1: The CAN1 received registers are frozen
Bit 24 DBG_I2CFMP_SMBUS_TIMEOUT: FMPI2C SMBUS timeout mode stopped when Core is
halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 23 DBG_I2C3_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 22 DBG_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted
1306/1324
28 27 26 25
Res.
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12 11 10 9
Res.
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24 23 22
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8 7 6
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RM0430 Rev 8
21 20 19 18
Res. Res. Res.
rw
5 4 3 2
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RM0430
17 16
Res. Res.
1 0
rw rw