Pin Placement For Differential Channels; Serdes Pin Pairs For Soft-Cdr Mode - Intel Agilex User Manual

5.6.2. Pin Placement for Differential Channels

Each GPIO sub-bank contains its own PLL. A PLL can drive all receiver and transmitter
channels in the same sub-bank, and transmitter channels in adjacent I/O sub-banks.
However, the individual PLL cannot drive receiver channels in another I/O sub-bank or
transmitter channels in non-adjacent I/O sub-banks.
The pin index number 0-47 and pin index number 48-95 from device pin out files are
respectively assigned to bottom sub-bank and top sub-bank in single GPIO bank.
Refer to External Memory Interface Pin Placement Requirements for more information
on the sub-bank arrangement for each I/O bank.
PLLs Driving DPA-Enabled Differential Receiver Channels
For differential receivers, the PLL can drive all channels in the same I/O sub-bank but
cannot drive across banks.
Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase
of the clock to the data phase of its associated channel.
DPA usage adds some constraints to the placement of high-speed differential receiver
channels. The Intel Quartus Prime compiler automatically checks the design and
issues error messages if there are placement guidelines violations. Adhere to the
guidelines to ensure proper high-speed I/O operation.
PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels in
LVDS SERDES Interface Spanning Multiple I/O Banks
If you use both differential transmitter and DPA-enabled receiver channels in a bank,
the PLL can drive the transmitters at the adjacent I/O banks, but only the receivers in
its own I/O sub-bank.
Related Information
External Memory Interface Pin Placement Requirements

5.6.3. SERDES Pin Pairs for Soft-CDR Mode

You can use only specific SERDES pin pairs in soft-CDR mode. Refer to the pinout file
of each device to determine the SERDES pin pairs that support the soft-CDR mode.
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Intel Agilex General Purpose I/O and LVDS SERDES User Guide
54
5. Intel Agilex High-Speed SERDES I/O Architecture
on page 30
UG-20214 | 2019.04.02
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