Dmac - Renesas M16C Series User Manual

M30240 Group

1.2.19 DMAC

This microcomputer has two DMAC (direct memory access controller) channels that allow data to be
sent to memory without using the CPU.Table 1.15 shows the DMAC specifications. Figure 1.53 shows
the block diagram of the DMAC. Figure 1.54, Figure 1.55 and Figure 1.56 show the registers used by
the DMAC.
Table 1.15: DMAC Specifications
Item
Number of channels
Transfer memory space
Maximum number of bytes
transferred
DMA request sources
Channel priority
Transfer unit
Transfer address direction
Transfer modes
DMA interrupt request generation
timing
DMA startup
DMA shutdown
Forward address pointer and
reload timing for transfer counter
Writing to register
Reading the register
Note: DMA transfers are not affected by the interrupt enable flag (I-FLAG) of any interrupt or by the interrupt priority level.
Rev.1.00 Sep 24, 2003 Page 60 of 360
2 (cycle steal method)
•From any SFR, RAM, or ROM address to a fixed address
•From a fixed address to any SFR or RAM address
•From a fixed address to a fixed address
(Note that DMA-related registers [0020
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4
Timer B0 to timer B1
UART0 transmission and reception
UART1 transmission and reception
UART2 transmission and reception
A-D conversion complete
USB function
Software triggers
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
8 bits or 16 bits
forward/fixed (forward direction cannot be specified for both source and destination
simultaneously)
•Single transfer mode
The DMA enable bit is cleared and transfer ends when an underflow occurs in the
transfer counter.
•Repeat transfer mode
When an underflow occurs in the transfer counter, the value in the transfer counter
reload register is loaded into the transfer counter and the DMA transfer is repeated
When an underflow occurs in the transfer counter
•Single transfer mode
Transfer starts when the DMA is requested after "1" is written to the DMA enable bit
•Repeat transfer mode
Transfer starts when the DMA is requested after "1" is written to the DMA enable bit
or after an underflow occurs in the transfer counter
•When "0" is written to the DMA enable bit
•When, in single transfer mode, an underflow occurs in the transfer counter
When DMA transfer starts, the value of whichever of the source or destination pointer that is set
up as the forward pointer is loaded into the forward address pointer. The value in the transfer
counter reload register is loaded into the transfer counter.
Registers specified for forward direction transfer are always write-enabled.
Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0".
Can be read at any time. However, when the DMA enable bit is "1", reading the register sets up
as the forward register is the same as reading the value of the forward address pointer.
Specification
to 003F ] cannot be accessed)
16 16
DMAC