Chip Select Control Register (Cscr) - Hitachi H8/3008 Hardware Manual

Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT
pin.
Bit 0
WAITE
0
1
6.2.6

Chip Select Control Register (CSCR)

CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
to CS
(CS ).
7 4
If output of a chip select signal CS
corresponding pin functions a chip select signal (CS
settings.
Bit 7
CS7E
Initial value 0
Read/Write R/W
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of
the corresponding chip select signal.
Bit n
CSnE
0
1
Note: n = 7 to 4
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1.
Description
WAIT pin wait input is disabled, and the WAIT pin can be used as an
input/output port
WAIT pin wait input is enabled
to CS
7
6 5
CS6E CS5E
0 0
R/W R/W
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
Description
Output of chip select signal CSn is disabled
Output of chip select signal CSn is enabled
is enabled by a setting in this register, the
4
to CS
) output regardless of any other
7 4
4 3
CS4E
—
0 1
R/W —
(Initial value)
2 1
— —
1 1
— —
Reserved bits
(Initial value)
0
—
1
—
111