Microblaze I/O Overview - Xilinx MicroBlaze Reference Manual

Chapter 3: MicroBlaze Signal Interface Description

MicroBlaze I/O Overview

The core interfaces shown in
Instruction-side
bus interface
M_AXI_IC
M_ACE_IC
IXCL_M
IXCL_S
M_AXI_IP
IPLB
Bus
IF
ILMB
Optional MicroBlaze feature
96
Send Feedback
Figure 3-1
M_AXI_DP: Peripheral Data Interface, AXI4-Lite or AXI4 interface
DPLB: Data interface, Processor Local Bus
DLMB: Data interface, Local Memory Bus (BRAM only)
M_AXI_IP: Peripheral Instruction interface, AXI4-Lite interface
IPLB: Instruction interface, Processor Local Bus
ILMB: Instruction interface, Local Memory Bus (BRAM only)
M0_AXIS..M15_AXIS: AXI4-Stream interface master direct connection interfaces
S0_AXIS..S15_AXIS: AXI4-Stream interface slave direct connection interfaces
MFSL 0..15: FSL master interfaces
DWFSL 0..15: FSL master direct connection interfaces
SFSL 0..15: FSL slave interfaces
DRFSL 0..15: FSL slave direct connection interfaces
DXCL: Data side Xilinx CacheLink interface (FSL master/slave pair)
M_AXI_DC: Data side cache AXI4 interface
M_ACE_DC: Data side cache ACE interface
IXCL: Instruction side Xilinx CacheLink interface (FSL master/slave pair)
M_AXI_IC: Instruction side cache AXI4 interface
M_ACE_IC: Instruction side cache ACE interface
Core: Miscellaneous signals for: clock, reset, debug, and trace
Memory Management Unit (MMU)
ITLB
Program
Counter
Special
Purpose
Registers
Branch
Target
Cache
Instruction
Buffer
Instruction
Decode
Figure 3-1: MicroBlaze Core Block Diagram
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and the following Table 3-1
UTLB
DTLB
ALU
Shift
Barrel Shift
Multiplier
Divider
FPU
Register File
32 X 32b
MicroBlaze Processor Reference Guide
are defined as follows:
Data-side
bus interface
M_AXI_DC
M_ACE_DC
DXCL_M
DXCL_S
M_AXI_DP
DPLB
DLMB
Bus
IF
M0_AXIS..
M15_AXIS
S0_AXIS..
S15_AXIS
MFSL 0..15
DWFSL 0..15
SFSL 0..15
DRFSL 0..15
UG081 (v14.7)
or
or