Dma Transfer Cycles - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)
14.2

DMA Transfer Cycles

Any combination of even or odd transfer read and write addresses is possible. Table 14.2 lists the DMA Transfer
Cycles. Table 14.3 lists the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles × j + No. of write cycles × k
Table 14.2 DMA Transfer Cycles
Transfer Unit Bus Width
8-bit Transfers 16-bit
(DMBIT= 1) (BYTE= L)
8-bit
(BYTE = H)
16-bit Transfers 16-bit
(DMBIT= 0) (BYTE = L)
8-bit
(BYTE = H)
— : This condition does not exist.
Table 14.3 Coefficient j, k
Internal Area
Internal ROM,
RAM
With
No Wait
Wait
j 1
k 1
NOTES:
1. Depends on the set value of CSE register.
2. Depends on the set value of PM20 bit in the PM2 register.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Access
Address
Even
Odd
Even
Odd
Even
Odd
Even
Odd
SFR
1-Wait 2-Wait
(2) (2)
2 2 3
2 2 3
Page 134 of 390
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Single-Chip Mode
No. of Read No. of Write
Cycles Cycles
1 1
1 1
— —
— —
1 1
2 2
— —
— —
External Area
Separate Bus
With Wait
No
Wait
1-Wait 2-Wait
1 2 3
2 2 3
Memory Expansion Mode
Microprocessor Mode
No. of Read No. of Write
Cycles
1
1
1
1
1
2
2
2
Multiplex Bus
(1)
With Wait
3-Wait 1-Wait 2-Wait
4 3 3
4 3 3
010-62245566 13810019655
14. DMAC
Cycles
1
1
1
1
1
2
2
2
(1)
3-Wait
4
4