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M16C/6N Group (M16C/6NK, M16C/6NM)
12.2 DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible.
Table 12.2 shows the number of DMA transfer cycles. Table 12.3 shows the coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k
Table 12.2 DMA Transfer Cycles
Transfer Unit
8-bit Transfer
(BYTE = L)
(DMBIT =1)
(BYTE= H)
16-bit Transfer
(BYTE =L)
(DMBIT = 0)
(BYTE = H)
-: This condition does not exist.
NOTE:
1. Not available memory expansion and microprocessor modes in T/V-ver..
Table 12.3 Coefficient j, k
Internal Area
Internal ROM, RAM
No Wait With Wait 1 Wait
j
1
2
k
1
2
NOTES:
1. Depends on the set value of the PM20 bit in the PM2 register.
2. Depends on the set value of the CSE register.
3. Not available external area in T/V-ver..
Rev.2.00
Nov 28, 2005
REJ09B0124-0200
Bus Width
Access Address
16 bits
Even
Odd
8 bits
Even
Odd
16 bits
Even
Odd
8 bits
Even
Odd
SFR
(1)
(1)
2 Waits
No Wait
2
3
1
2
3
2
page 110 of 378
Single-chip Mode
No. of Read No. of Write No. of Read No. of Write
Cycles
Cycles
1
1
1
1
-
-
-
-
1
1
2
2
-
-
-
-
External Area
Separate Bus
(2)
With Wait
1 Wait 2 Waits 3 Waits 1 Wait 2 Waits 3 Waits
2
3
4
2
3
4
12. DMAC
Memory Expansion Mode
(1)
Microprocessor Mode
Cycles
Cycles
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
(3)
Multiplexed Bus
(2)
With Wait
3
3
4
3
3
4
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