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Peripherals
SCK
SST
SIOF
SO
SCK
SI
SO
SCK
SI
SO
DI7 to DI0 indicate input data, and DO7 to DO0 indicate output data.
HARDWARE CONFIGURATION
[When transfer suspended]
#0
#1
#2
Note: When data is written at the SDR, the output data changes at the
falling edge of the external-clock pulse.
Fig. 2.19 Shift Start/Stop Timing
(e) Input/output shift timing
Data is output from the serial output pin (SO) at the falling edge of the shift-
clock pulse, and is input from the serial input pin (SI) to the SDR at the
rising edge of the shift-clock pulse.
a. LSB first (BDS = 0)
#0
#1
SO output
#0
#1
#2
b. MSB first (BDS = 1)
#7
#6
SO output
#7
#6
#5
Fig. 2.20 Input/Output Shift Timing
2– 55
#3
#4
#5
SI input
#2
#3
#4
#3
#4
#5
SI input
#5
#4
#3
#2
#4
#3
#2
#5
#6
#7
#6
#7
#1
#0
#1
#0
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