Near-End Pcs Loopback; Near-End Pma Loopback - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features

Near-end PCS Loopback

In the Near-end PCS loopback mode, data is generated by user logic and looped back
internal to the PCS. Then the data is checked by the user logic. Any PCS operating mode
(8B/10B mode, raw mode, etc.) can be used. The PMA is not used.
Figure 2-13
X-Ref Target - Figure 2-13
TXN/TXP
RX
RXN/RXP
Buffer

Near-end PMA Loopback

This mode uses either user logic or the PRBS generator/checker to generate and check the
test data. The serial loopback path to the RX buffer is either after the TX pre-driver (before
the TX buffer) or after the TX buffer. In this mode, the operation for all enabled PCS and
PMA functional blocks in the transmitter and receiver channel can be verified.
Figure 2-14
X-Ref Target - Figure 2-14
TXN/TXP
Serial
Loopback
RXN/RXP
68
shows the PCS internal loopback path.
PMA
Serializer
TX
Buffer
Deserializer
CDR
DFE
Figure 2-13: Near-end PCS Loopback
shows a simplified block diagram of the Near-end PMA loopback mode.
PMA
Pre-emphasis
TX
Buffer
CDR
RX
Buffer
DFE
Linear EQ
Figure 2-14: Near-end PMA Loopback
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PCS
Serializer
Deserializer
Virtex-6 FPGA GTH Transceivers User Guide
TXDATA
PRBS
Generator
RXDATA
PRBS
Checker
UG371_c2_10_120109
PCS
TXDATA
PRBS
Generator
RXDATA
PRBS
Checker
UG371_c2_11_120109
UG371 (v2.0) February 16, 2010