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8.3.3.9
RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22
The Receiver Frame Sync Signal Direction (RFSD) bit selects the source of the receiver frame sync signal when in the asynchronous mode
(SYN=0) and the IF1/OF1/Transmitter Buffer Enable flag direction in the synchronous mode (SYN=1).
In the asynchronous mode, when RFSD is set, the internal clock generator becomes the source of the receiver frame sync and is the output on
the FSR pin. In the asynchronous mode, when RFSD is cleared, the receiver frame sync source is external; the internal clock generator is
disconnected from the FSR pin, and an external clock source may drive this pin.
In the synchronous mode when RFSD is set, the FSR pin becomes the OF1 output flag or the Transmitter Buffer Enable, according to the
TEBE control bit. If RFSD is cleared, the FSR pin becomes the IF1 input flag. See
8.3.3.10
RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23
The Receiver High Frequency Clock Direction (RHCKD) bit selects the source of the receiver high frequency clock when in the asynchronous
mode (SYN=0) and the IF2/OF2 flag direction in the synchronous mode (SYN=1).
In the asynchronous mode, when RHCKD is set, the internal clock generator becomes the source of the receiver high frequency clock and is
the output on the HCKR pin. In the asynchronous mode, when RHCKD is cleared, the receiver high frequency clock source is external; the
internal clock generator is disconnected from the HCKR pin, and an external clock source may drive this pin.
When RHCKD is cleared, HCKR is an input; when RHCKD is set, HCKR is an output.
In the synchronous mode when RHCKD is set, the HCKR pin becomes the OF2 output flag. If RHCKD is cleared, the HCKR pin becomes
the IF2 input flag. See
Figure 8-1
8.3.4
ESAI Receive Control Register (RCR)
The read/write Receive Control Register (RCR) controls the ESAI receiver section. Interrupt enable bits for the receivers are provided in this
control register. The receivers are enabled in this register (0,1,2 or 3 receivers can be enabled) if the input data pin is not used by a transmitter.
Operating modes are also selected in this register.
Freescale Semiconductor
Table 8-8. FSR Pin Definition Table
Control Bits
SYN
TEBE
0
X
0
X
1
0
1
0
1
1
1
1
and
Figure
8-9.
Table 8-9. HCKR Pin Definition Table
Control Bits
SYN
RHCKD
0
0
0
1
1
0
1
1
DSP56374 Users Guide, Rev. 1.2
Figure 8-1
and
Figure
FSR Pin
RFSD
0
FSR input
1
FSR output
0
IF1
1
OF1
0
reserved
1
Transmitter Buffer
Enable
HCKR PIN
HCKR input
HCKR output
IF2
OF2
ESAI Programming Model
8-8.
8-19
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