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show pxf dma
The following example shows a typical display for the dma registers option:
Router# show pxf dma registers
PXF DMA PCI Registers:
Vendor and Device ID: 0x00001137
Command and Status: 0x02A00147
Revision ID and Class Code: 0x00000000
Cache Latency and Header BIST: 0x00003010
Base Address Registers:
CIS Pointer Register: 0x00000000
Subsystem Vendor ID and Subsystem ID: 0x00000000
Expansion ROM Base Address: 0x00000000
Interrupt Grant Latency Register: 0x00000000
PXF DMA General Purpose Registers:
Soft Reset: 0x000000FF, Line Card Reset: 0x00000000
PXF DMA Part Number: 0x08034101, PXF DMA Version 0x00000003
Event1: 0x00000000, Halt Mask1: 0x6500FE00, Fault Mask1: 0x6400B400
Event2: 0x00000008, Halt Mask2: 0x0000003F, Fault Mask2: 0x0000000C
Event3: 0x00000000, Halt Mask3: 0x0000FFFF, Fault Mask3: 0x0000C1CF
Debug Registers:
FTBB Registers:
FBB Registers:
TTC Registers:
FTC Control: 0x00000070
OQC Registers:
SDRAM Registers:
To RP Registers:
From RP Registers:
RP Debug Out: 0x00000000
Debug Registers:
FBB Rx Iron Bus Engine Debug Resource 04: 0x00000000
FBB Rx Iron Bus Engine Debug Resource 06: 0x00000000
FBB Rx Iron Bus Engine Debug Resource 07: 0x00000000
FBB Rx Iron Bus Engine Debug Resource 11: 0x00000000
FBB Rx Iron Bus Engine Debug Resource 12: 0x00000000
FBB Rx Iron Bus Engine Debug Resource 13: 0x00000000
FBB Rx Iron Bus Engine Debug Resource 14: 0x00000000
FBB Rx Iron Bus Engine Debug Resource 15: 0x00000000
OQC Output Command Queue 03 Debug Data: 0x00001040, qN_entry_cnt[5:0]: 0
OQC Output Command Queue 05 Debug Data: 0x00001040, qN_entry_cnt[5:0]: 0
OQC Output Command Queue 06 Debug Data: 0x00001040, qN_entry_cnt[5:0]: 0
OQC Output Command Queue 10 Debug Data: 0x00001040, qN_entry_cnt[5:0]: 0
OQC Output Command Queue 11 Debug Data: 0x00001040, qN_entry_cnt[5:0]: 0
OQC Output Command Queue 12 Debug Data: 0x00001040, qN_entry_cnt[5:0]: 0
OQC Output Command Queue 13 Debug Data: 0x00001040, qN_entry_cnt[5:0]: 0
Cisco Broadband Cable Command Reference Guide
4-82
BAR0: 0x9C000000, BAR1: 0x00000000, BAR2: 0x00000000
BAR3: 0x00000000, BAR4: 0x00000000, BAR5: 0x00000000
Address: 0x000000CE, Out: 0x00001E11, Compare: 0x00000000
Control1: 0xE0404060, Control2: 0x44444040, Control3: 0x00000040
Flow: 0x00000001
Length Error: 0x00000000, Multi-SOP Error: 0x00000000
CRC Error: 0x00000000, IPM Overrun Error: 0x00000000
Control: 0xFF000022, Pad1: 0xAAAAAAAA, Pad2: 0x00000000
Control: 0x000002D0, Priority: 0x00007C40, Status: 0x00000000
Control: 0x00272400, Status: 0x00000000
ECC Override: 0x00000000, Error Address 0x00000000
Window: 0x00000007, Timing: 0x000061A8
Descriptor Ring Base Address: 0x0B2A6CC0, Buffer Size: 0x00000200
Descriptor Status: 0x00E00008, DMA Control: 0x00103E04
Descriptor Word0: 0x08AA9740, Descriptor Word1 0x02000002
Descriptor Ring Base Address: 0x0B2A6F00
Descriptor Status: 0x00D0000C, DMA Control: 0x01007E04
Descriptor Word0: 0x00000000, Descriptor Word1: 0x00000000
Chapter 4
Commands for the Cisco uBR10012 Router
OL-1581-08
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