Rtc Initialization And Status Register (Rtc_Isr) - ST STM32F205 series Reference Manual

RM0033
Note: WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
To avoid spuriously setting of TSF, TSE must be reset when TSEDGE is changed.
This register is write protected. The write access procedure is described in
write protection on page
22.6.4

RTC initialization and status register (RTC_ISR)

Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset value: Not affected except INIT, INITF and RSF which are cleared to 0.
31 30 29
15 14 13
TAMP
Res. Res. TSOVF
1F
rc_w0 rc_w0
Bits 31:14 Reserved
Bit 13 TAMP1F: Tamper detection flag
Bit 12 TSOVF: Timestamp overflow flag
Bit 11 TSF: Timestamp flag
Bit 10 WUTF: Wakeup timer flag
Bit 9 ALRBF: Alarm B flag
574.
28 27 26 25
12 11 10 9
TSF WUTF ALRBF ALRAF
rc_w0 rc_w0 rc_w0
This flag is set by hardware when a tamper detection event is detected.
It is cleared by software writing 0.
This flag is set by hardware when a timestamp event occurs while TSF is already set.
This flag is cleared by software by writing 0. It is recommended to check and then clear
TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a
timestamp event occurs immediately before the TSF bit is cleared.
This flag is set by hardware when a timestamp event occurs.
This flag is cleared by software by writing 0.
This flag is set by hardware when the wakeup auto-reload counter reaches 0.
This flag is cleared by software by writing 0.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
Alarm B register (RTC_ALRMBR).
This flag is cleared by software by writing 0.
24 23 22
8 7 6
INIT INITF
rc_w0 rw r rc_w0
RM0033 Rev 8
Real-time clock (RTC)
RTC register
21 20 19 18
5 4 3 2
WUT
RSF INITS Res.
WF
r r
17 16
Res.
1 0
ALRB ALRA
WF WF
r r
587/1378
597