Development Board Setup; Applying Power To The Development Board - Intel Stratix 10 GX FPGA User Manual

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UG-20046 | 2020.04.02
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3. Development Board Setup

3.1. Applying Power to the Development Board

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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
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This chapter describes how to apply power to the development board and provides
default switch and jumper settings.
This development kit is designed to operate in two modes:
1. As a PCIe* add-in card
When operating the card as a PCIe system, insert the card into an available PCIe
slot and connect a 2x4 and 2x3 pin PCIe power cable from the system to power
connectors at J26 and J27 of the board respectively.
Note: When operating as a PCIe add-in card, the board does not power on unless
power is supplied to J26 and J27.
2. In bench-top mode
In Bench-top mode, you must supply the board with provided power 240W power
supply connected to the power connector J27. The following describes the
operation in bench-top mode.
This development board ships with its switches preconfigured to support the design
examples in the kit.
If you suspect that your board may not be correctly configured with the default
settings, follow the instructions in the Default Switch and Jumper Settings section of
this chapter.
1. The development board ships with design examples stored in the flash memory
device. To load the design stored in the factory portion of the flash memory, verify
SW3.3 is set to ON. This is the default setting.
2. Connect the supplied power supply to an outlet and the DC Power Jack (J27) on
the FPGA board.
Note: Use only the supplied power supply. Power regulation circuits on the board
can be damaged by power supplies with greater voltage.
3. Set the power switch (SW7) to the ON position.
When the board powers up, the parallel flash loader (PFL) on the MAX
design from flash memory and configures the FPGA. When the configuration is
complete, green LEDs illuminate signaling the device configured successfully. If the
configuration fails, the red LED illuminates.
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