Timing Of Clearing Of Status Flags - Hitachi H8/3006 Hardware Manual

φ
16TCNT
Overflow
signal
OVF
OVI
9.5.2

Timing of Clearing of Status Flags

If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 9.36 shows the timing.
φ
Address
IMF, OVF
Figure 9.35 Timing of Setting of OVF
Figure 9.36 Timing of Clearing of Status Flags
TISR write cycle
T T
1 2
TISR address
T
3
333