System Clock (Ck_Sys) Selection - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352

System Clock (CK_SYS) Selection

After the system reset occurs, the default system clock source CK_SYS will be the high speed
internal RC oscillator HSI. The CK_SYS may come from the HSI, HSE, LSE, LSI or PLL output
clock and it can be switched from one clock source to another by changing the System Clock
Switch bits, SW, in the Global Clock Control Register GCCR. The system will still run under
the original clock until the destination clock gets ready when the SW value is changed. The
corresponding clock ready status bit in the Global Clock Status Register (GCSR) will indicate
whether the selected clock is ready to use or not. The CKCU also contains the clock source status
bits in the Clock Source Status Register (CKST) to indicate which clock is currently used as the
system clock. If a clock source or the PLL output clock is uses as the system clock source, it is not
possible to stop it. More details about the clock enable function is described in the following.
If any event in the following occurs, the HSI will be enabled.
▄
Enable PLL and configure its source clock to HSI. (PLLEN, PLLSRC)
▄
Enable Clock monitor. (CKMEN)
▄
Configure clock switch register to HSI. (SW)
▄
Configure HSI enable register to 1. (HSIEN)
If any event in the following occurs, the HSE will be enabled.
▄
Enable PLL and configure its source clock to HSE. (PLLEN, PLLSRC)
▄
Configure clock switch register to HSE. (SW)
▄
Configure HSE enable register to 1. (HSEEN)
If any event in the following occurs, the PLL will be enabled.
▄
Enable USB Enable register. (USBEN)
▄
Configure clock switch register to PLL (SW)
▄
Configure PLL enable register to 1. (PLLEN)
The system clock selection programming guide is listed in the following.
1. Enable any clock source which will become the system clock or PLL input clock.
2. Configuring the PLLSRC register after the ready flags of both HSI and HSE are asserted,
3. Configuring the SW register to change the system clock source will occur after the corresponding
ready flag of the clock source is asserted. Note that the system clock will be forced to HSI if
the clock monitor is enabled and the PLL output or HSE clock configured as the system clock is
stuck at 0 or 1.
Rev. 1.30 90 of 656 September 28, 2018