32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52220/HT32F52230
CTS Flow Control
If the hard flow control function is enabled, the URTXEN bit in the USRCR register will be
controlled by the USART CTS input signal. If the USART CTS pin is forced to a logic low state,
the URTXEN bit will automatically be set to 1 to enable the data transmission. However, if the
USART CTS pin is forced to a logic high state, the URTXEN bit will be cleared to 0 and then the
data transmission will also be disabled.
When the USART CTS pin is forced to a logic high state during a data transmission period, the
current data transmission will be continued until the stop bit is completed. The Figure 114 shows an
example of the communication with CTS flow control.
Start Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
CTS
4
TXFS[3:0]
Figure 111. USART CTS Flow Control
IrDA
The USART IrDA mode is provided as a half-duplex point-to-point wireless communication
interface.
The USART module includes an integrated modulator and demodulator which allow a wireless
communication using infrared transceivers. The transmitter specifies a logic data '0' as a 'high'
pulse and a logic data '1' as a 'low' level while the Receiver specifies a logic data '0' as a 'low'
pulse and a logic data '1' as 'high' level in the IrDA mode.
Rev. 1.10
Parity Bit
Start Bit
Bit N
Stop Bit
Idle
Bit 0
N=6~8
332 of 366
Parity Bit
Bit 1
Bit 2 Bit 3 Bit 4
Bit N
N=6~8
3
November 09, 2018
Start Bit
Stop
Bit 0
Bit
2
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