Slave Controller; Figure 41. Slave Controller Diagram; Figure 42. Gptm In Restart Mode - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352

Slave Controller

The GPTM can be synchronized with an external trigger in several modes including the Restart
mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR
register. The trigger input of these modes comes from the STI signal which is selected by the
TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in
the accompanying sections.
Trigger Controller

Figure 41. Slave Controller Diagram

Restart Mode
The counter and its prescaler can be reinitialized in response to a rising edge of the STI signal.
When a STI rising edge occurs, the update event software generation bit named UEVG will
automatically be asserted by hardware and the trigger event flag will also be set. Then the counter
and prescaler will be reinitialized. Although the UEVG bit is set to 1 by hardware, the update event
does not really occur. It depends upon whether the update event disable control bit UEVDIS is set
to 1 or not. If the UEVDIS is set to 1 to disable the update event to occur, there will no update event
be generated, however the counter and prescaler are still reinitialized when the STI rising edge
occurs. If the UEVDIS bit in the CNTCFR register is cleared to enable the update event to occur,
an update event will be generated together with the STI rising edge, then all the preloaded registers
will be updated.

Figure 42. GPTM in Restart Mode

Rev. 1.30
STI
Timer Counter Reload Register CRR = 32
STI source signal
(polarity=0)
STI source signal
(polarity=1)
STI
CK_CNT
UEVG bit
(reset counter)
CNTR
27 28
(Up-counting)
CNTR
27 26
(Down-counting)
TEVIF
237 of 656
Trigger Event
Slave
Controller
Reset/Stop/Start Counter
SMSEL Restart/Pause/Trigger Mode
Sync.
Trigger Event
0
29 30 31
25 24 23 32
1 2
31 30
September 28, 2018