Apb Clock Control Register 1 - Apbccr1 - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
APB Clock Control Register 1 – APBCCR1
This register specifies the APB peripherals clock enable control bits.
Offset: 0x030
Reset value: 0x0000_0000
31
Reserved SCTM1EN SCTM0EN
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved VDDREN
Type/Reset RW
Bits Field
[29] SCTM1EN
[28] SCTM0EN
[24] ADCCEN
[16] BFTMEN
[8] GPTMEN
[6] VDDREN
[4] WDTREN
Rev. 1.10
30 29 28
RW 0 RW
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved WDTREN
0 RW
Descriptions
SCTM1 Clock Enable
0: SCTM1 clock is disabled
1: SCTM1 clock is enabled
Set and reset by software.
SCTM0 Clock Enable
0: SCTM0 clock is disabled
1: SCTM0 clock is enabled
Set and reset by software.
ADC Controller Clock Enable
0: ADC clock is disabled
1: ADC clock is enabled
Set and reset by software.
BFTM Clock Enable
0: BFTM clock is disabled
1: BFTM clock is enabled
Set and reset by software.
GPTM Clock Enable
0: GPTM clock is disabled
1: GPTM clock is enabled
Set and reset by software.
V Domain Clock Enable for Registers Access
DD
0: V Domain Register access clock is disabled
DD
1: V Domain Register access clock is enabled
DD
Set and reset by software.
Watchdog Timer Clock Enable for Registers Access
0: Register access clock is disabled
1: Register access clock is enabled
Set and reset by software.
89 of 366
27 26
Reserved
0
19 18
11 10
3 2
Reserved
0
25 24
ADCCEN
RW 0
17 16
BFTMEN
RW 0
9 8
GPTMEN
RW 0
1 0
November 09, 2018