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SH7211 Group
Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)
Introduction
This application note describes the operation of the DMAC, and is intended for reference to help in the design of user
software.
Target Device
SH7211
Contents
1.
Introduction ....................................................................................................................................... 2
2.
Description of Sample Application .................................................................................................... 3
3.
Documents of Reference ................................................................................................................ 11
REJ06B0732-0100/Rev.1.00
March 2008
APPLICATION NOTE
Page 1 of 13
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Summary of Contents for Renesas REJ06B0732-0100
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Page 1: Application Note
This application note describes the operation of the DMAC, and is intended for reference to help in the design of user software. Target Device SH7211 Contents Introduction ... 2 Description of Sample Application ... 3 Documents of Reference ... 11 REJ06B0732-0100/Rev.1.00 APPLICATION NOTE March 2008 Page 1 of 13... - Page 2 • Operating Frequency: Internal clock Bus clock Peripheral clock • C Compiler: SuperH RISC engine family C/C++ compiler package Ver.9.01, from Renesas Technology REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 160 MHz 40 MHz 40 MHz...
- Page 3 Priority level Interrupt request External request detection Transfer request acknowledge signal/transfer end signal REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Description 8 (CH0 to CH7) Only 4 (CH0 to CH3) can receive external requests. 4 Gbytes Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword ×...
- Page 4 DREQ Bus cycle Figure 2 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection) REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Bus mastership returned to CPU once DMAC...
- Page 5 RSAR: DMA reload source address register SAR: DMA source address register RDAR: DMA reload destination address register DEIn: DAR: DMA destination address register REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Iteration control Register control Start-up control...
- Page 6 Interrupt request DMAC [Legend] SAR:Source address register DAR:Destination address register REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Auto request mode 4 bytes 128 transfers (128 × data length of 4 bytes = 512-byte data) Dual address mode...
- Page 7 DMAC0.CHCR.BIT.DE = 1 Transfer completed? DMAC0.CHCR.BIT.DE = 0 * In this sample application, sleep processing is performed after the main routine is complete. REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) [1] Cancel module standby mode Activate the DMAC...
- Page 8 Set DMA channel control register (CHCR_0) Set DMA operation register (DMAOR) Figure 6 Flowchart of Initializing DMAC REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) [1] Disable DMA transfer Set the DE (DMA enable) bit to 0 Disable DMA transfer...
- Page 9 Table 6 Settings of Standby Control Register Register Name Address Standby control H’FFFE0018 register 2 (STBCR2) REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Setting Value Description H’1303 CKOEN = “B’1”: output clocks STC[1:0] = “B’00”: frequency multiplication ratio of PLL circuit ×...
- Page 10 H’FFFE1008 register 0 (DMATCR) DMA channel control H’FFFE100C register 0 (CHCR) H’FFFE1200 DMA operation register (DMAOR) REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Setting Value Description H’FFF81000 Transfer source start address H’FFF82000 Transfer destination start address D’128...
- Page 11 Documents for Reference • Software Manual SH-2A, SH2A-FPU Software Manual The most up-to-date version of this document is available on the Renesas Technology Website. • Hardware Manual SH7211 Group Hardware Manual The most up-to-date version of this document is available on the Renesas Technology Website.
- Page 12 Website and Support Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com Revision Record Description Rev. Date Page 1.00 Mar.21.08 — All trademarks and registered trademarks are the property of their respective owners. REJ06B0732-0100/Rev.1.00 Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)
- Page 13 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.