Altera cyclone V Technical Reference page 3485

cv_5v4
2016.10.28
• Tool name—The name of the simulation tool
• Format for output netlist
• Output directory
c. Click OK.
5. To create the post-fitter simulation model with Quartus Prime EDA Netlist Writer, perform the
following steps:
a. Click Start in the Processing menu.
b. Click Start EDA Netlist Writer.
Related Information
Quartus Prime Help
Post-Fit Simulation Files
Post-fit simulation is the simulation of the netlist generated from the original RTL design after it has been
mapped, synthesized, and fit. The netlist represents the actual hardware and its connections as they appear
in the FPGA. Quartus Prime generates the netlist and can generate a Standard Delay Format (.sdf) file
with the timing information for all connections. The simulation can be functional only (without the
timing information) where all wires and gates take zero time, or it can be a timing simulation where the
time for all transitions is based on the SDF information.
Post-fit simulation can serve a number of different purposes. It can be used to perform a dynamic verifica‐
tion of the timing of the design, or it can be used to verify the functional correctness of either the design,
the compilation flow (in particular, the fitter)​, or both.
This table uses the following symbols:
• <ACDS install> = Altera Complete Design Suite installation path
• <Avalon Verification IP> = <ACDS install>/ip/altera/sopc_builder_ip/verification
• <AXI Verification IP> = <ACDS install>/ip/altera/mentor_vip_ae
• <HPS Post-fit Sim> = <ACDS install>/ip/altera/hps/postfitter_simulation
• <Device Sim Lib> = <ACDS install>/quartus/eda/sim_lib
Table 29-11: Post-Fit Simulation Files
Library
Altera Verifica‐
tion IP Library
Avalon Clock
Source BFM
Avalon Reset
Source BFM
Avalon MM
Slave BFM
Simulating the HPS Component
Send Feedback
Directory
<Avalon Verification IP>/lib/
<Avalon Verification IP>/
altera_avalon_clock_source/
<Avalon Verification IP>/
altera_avalon_reset_source/
<Avalon Verification IP>/
altera_avalon_mm_slave_bfm/
Post-Fit Simulation Files
File
verbosity_pkg.sv
avalon_mm_pkg.sv
avalon_utilities_pkg.sv
altera_avalon_clock_source.sv
altera_avalon_reset_source.sv
altera_avalon_mm_slave_bfm.sv
Altera Corporation
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