Boot Overview - Altera cyclone V Technical Reference

2016.10.28
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The Altera system-on-a-chip (SoC) device provides a variety of ways to boot the hard processor system
(HPS) and configure the FPGA portion.

Boot Overview

The boot flow of the HPS is a multi-stage process. Each stage is responsible for loading the next stage.
The first software stage is the boot ROM. The boot ROM code locates and executes the second software
stage, called the preloader. The preloader locates, and if present, executes the next software stage. The
preloader and subsequent software stages (if present) are collectively referred to as user software.
Only the boot ROM code is located in the HPS. Subsequent software is located external to the HPS and is
provided by users. The boot ROM code is only aware of the preloader and not aware of any potential
subsequent software stages.
The figure below illustrates the typical boot flow. However, there may be more or less software stages in the
user software than shown and the roles of the software stages may vary.
Figure A-1: Typical Boot Flow
Reset Boot ROM
FPGA Configuration Overview
After power is applied to the FPGA and HPS portion of the SoC, configuration may begin. The FPGA may
be configured through a variety of ways, such as through the HPS, JTAG, or an external host.
The control block (CB) in the FPGA portion of the device is responsible for obtaining an FPGA configura‐
tion image and configuring the FPGA. The FPGA configuration ends when the configuration image has
been fully loaded and the FPGA enters user mode. The FPGA configuration image is provided by users
and is typically stored in external non-volatile flash-based memory. The FPGA CB can obtain a configura‐
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