Function; Block Diagram; Spi Interface; Write Access - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
16.3.

Function

16.3.1.

Block Diagram

Figure 16-1 shows a block diagram of the host interface.
I ndigo
Host CPU
Host CPU
HOST_DI
HOST DI
HOST_DO
HOST DO
HOST_SCK
HOST SCK
HOST_XCS
HOST XCS
HOST_INT
HOST INT
16.3.2.

SPI Interface

16.3.2.1.

Write Access

Accesses from the host CPU to this module can arbitrarily use address byte lengths in a range of
1 to 4 bytes, as set. Also, the data byte length can be arbitrarily set in a range of 1 to 16 bytes.
This module provides a function to notify the host CPU with the result of write processing. It is
necessary to send a dummy write CMD after a normal write CMD. The host CPU serial clock is
maintained by sending dummy write CMDs. The result of write processing is sent with this clock.
The basic format of a write access is shown below.
Write
HOS T S C K
HOS T X C S
HOS T DI
C MD AB #0 AB #1
AD D 07-00 AD D 15-08
AB L AB L D B L D B L D B L R /W C N T C N T
AB L [1:0] Addres s B yte L ength : 1-4 B yte
D B L [2:0] D ata B yte L ength : 1-16B yte
R /W R ead or W rite s elec t
C NT [1:0] C ommand for c ontrol by HO S T
16-2
HOST-IF
HOST-IF
EXTIF CNT
EXTIF CNT
RxBuff
RxBuff
(32bit*
(32bit*
4word)
4word)
TxBuff
TxBuff
(32bit*
(32bit*
4word)
4word)
Figure 16-1 Host interface block diagram
AB #2 AB #3 D B #0 D B #1 D B #2
AD D 23-16 AD D 31-24 D T07-00 D T15-08 D T23-16
HOS T DO
01:1byte 10:2byte 11:3byte 00:4byte
see note.
1:W rite 0:R ead
10:R S T other:not R S T
Figure 16-2 Write access
AHB Data_Swap
AHB Data_Swap
Master
Master
INT
INT
Error Resp
Error Resp
Reset req
Reset req
interrupt
interrupt
CCNT:Chip Controller Module
CCNT :Chip Controller Module
CRG: Clock & Reset generator
CRG: Clock & Reset generator
D B #3 C MD C MD C MD
(D m yWrite (D m yWrite (D m yWrite
D T31-24
(DmyWr it e ) se t CMD_ DBL[ 2 :1 ] - > 0 ,0 ,0
S TA TUS S TA TUS S TA TUS
(WriteS ts 0 (WriteS ts 0 (WriteS ts 0 (WriteS ts
R x Tx S E R
1 1 1
R D Y R D Y R
AHB
AHB
BUS
B US
ix_HRESET
from
CRG
i_WSWAP
i_WSWAP
i_HWSWAP[1:0] to
i_HWSWAP[1:0] to
i_BSWAP CRG
i_BSWAP CRG
CCNT
CCNT
All_soft
All_soft
_Reset
_Reset
ox_HST_ASRST
ox_HST_ ASRST
o_HST_INT
o_HST_INT
status
status
to R-H Reg
Reg
from
from
internal
internal
m odule
module
INT
INT
C MD Nex t Read or Write Reques t (A c c es s )
(D m yWrite
LightGDC sends WriteSts0
until WriteSts becomes
WriteSts1.(Write complete!)
S TA TUS
1
R xR D Y 0:R eadS ts 0, 1:R eadS ts 1
T xR D Y 0:W riteS ts 0, 1:W riteS ts 1
1 1
S E R R 0:Nor, 1:E R R -R E S P