Table of Contents
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MB86R02 'Jade-D' Hardware Manual V1.64
1
Overview ....................................................................................................................................... 1-1
1.1
Features ............................................................................................................................. 1-1
1.2
Block Diagram .................................................................................................................... 1-3
1.2.1
Outline of each functional block ...................................................................................... 1-4
Function Summary of the Blocks ...................................................................................................... 1-6
1.3
Package Dimensions .......................................................................................................... 1-9
1.4
Pinning .............................................................................................................................. 1-10
1.5
Pin Assignment................................................................................................................. 1-10
1.5.1
Pin Assignment Table ................................................................................................... 1-12
1.5.2
Pin Multiplexing ............................................................................................................. 1-22
1.6
Pin Functional Description ................................................................................................ 1-31
2
System Configuration .................................................................................................................... 2-1
2.1
Typical Application ............................................................................................................. 2-1
3
Memory Map ................................................................................................................................. 3-1
3.1
Memory Map of LSI ............................................................................................................ 3-1
3.2
Register Access.................................................................................................................. 3-4
4
CPU (ARM926EJ-S core) ............................................................................................................. 4-1
4.1
Outline of ARM926EJ-S core ............................................................................................. 4-1
4.2
Features of ARM926EJ-S core .......................................................................................... 4-1
4.3
Block diagram of ARM926EJ-S core .................................................................................. 4-1
4.4
Configuration of ARM926EJ-S and ETM ........................................................................... 4-2
5
Clock Reset Generator (CRG) ...................................................................................................... 5-1
5.1
Outline ................................................................................................................................ 5-1
5.2
Features ............................................................................................................................. 5-1
5.3
Overview ............................................................................................................................. 5-2
5.4
Location in the device ......................................................................................................... 5-3
5.5
Operation ............................................................................................................................ 5-3
5.5.1
Reset Generation ............................................................................................................ 5-3
5.5.2
Clock Generation ............................................................................................................ 5-7
5.6
Registers .......................................................................................................................... 5-16
5.1.1.
Register list ................................................................................................................... 5-16
5.1.2.
PLL control register (CRPR) ......................................................................................... 5-18
5.1.3.
Watchdog timer control register (CRWR) ..................................................................... 5-21
5.1.4.
Reset/Standby control register (CRSR) ........................................................................ 5-23
5.1.5.
Clock divider control register A (CRDA) ....................................................................... 5-25
5.1.6.
Clock divider control register B (CRDB) ....................................................................... 5-27
5.1.7.
AHB (A) bus clock gate control register (CRHA) .......................................................... 5-28
5.1.8.
APB (A) bus clock gate control register (CRPA) .......................................................... 5-29
5.1.9.
Reserved control register (CRPB) ................................................................................ 5-30
5.1.10.
AHB (B) bus clock gate control register (CRHB) ...................................................... 5-31
5.1.11.
ARM core clock gate control register (CRAM) .......................................................... 5-32
5.1.12.
DPERI clock gate control register (CRDP0, CRDP1) ............................................... 5-32
5.1.13.
Clock Selector control register (CSEL) ..................................................................... 5-33
6
Spread Spectrum Clock Generator (SSCG) ................................................................................. 6-1
6.1
Position of Block in whole LSI ............................................................................................ 6-1
6.2
Features ............................................................................................................................. 6-1
6.2.1
Functional ....................................................................................................................... 6-1
6.2.2
Limitations ....................................................................................................................... 6-1
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