Common Control Register - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

18.7.8 Common control register

VCCC (Vdisp/Capture common control)
Register
DisplayBase0 + 0x7FF8
address
Bit number
31 30 29
Bit field name
reserve
R/W R0W0
0
Initial value
Bit 0 V0sr (Vdisp0 software reset)
Specifies whether or not to perform software reset for display controller 0. Reset
action is triggered by write of VCSR register. It is only specifying that this bit is written.
0:
1:
Bit 1 V1sr (Vdisp1 software reset)
Specifies whether or not to perform software reset for display controller 1. Reset
action is triggered by write of VCSR register. It is only specifying that this bit is written.
0:
1:
Bit 2 C0sr (Capture0 software reset)
Specifies whether or not to perform software reset for capture controller 0. Reset
action is triggered by write of VCSR register. It is only specifying that this bit is written.
0:
1:
Bit 3 C1sr (Capture1 software reset)
Specifies whether or not to perform software reset for capture controller 1. Reset
action is triggered by write of VCSR register. It is only specifying that this bit is written.
0:
1:
Bit 12 C0sel (Capture0 select)
Selects an input of capture controller 0 if A0sel=0.
This bit is ignored if A0sel=1, but set zero for ES1.
0:
1:
18-64
21 20 19 18 17
dis2s resv hmon
R0W0
RW RW
0 0 0
Performs no software reset.
Performs software reset.
Performs no software reset.
Performs software reset.
Performs no software reset.
Performs software reset.
Performs no software reset.
Performs software reset.
656 dedicated port (A0sel=0)
RGB/656 shared port (A0sel=0)
16 15 14 13 12 11 10
A1sel A0sel C1sel C0sel
RW RW RW RW
0 1 1 1 0
5 4 3 2 1
reserve C1sr C0sr V1sr
RW0 RW RW RW
0 0 0 0
0
V0sr
RW
0