Interrupt Vector Register (Vct) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

9.5.9 Interrupt vector register (VCT)

When it is assert (The IRQF bit of the IRQF register sets it to "1"), IRQ displays the interrupt vector
table to the interrupt source that should be processed in the ARM core as for the VCT register.
The priority of vector address is as follows.
•
In the source where the IRQ interrupt occurs, the priority of the interrupt source vector of the
high level rises most.
•
The address offset value rises the priority when the interrupt transmission source at this level
is caused at the same time and the small rises.
I
Address
FFFF_FE00
Bit 31 30 29
Name VCT31 VCT30 VCT29 VCT28 VCT27 VCT26 VCT25 VCT24 VCT23 VCT22 VCT21 VCT20 VCT19 VCT18 VCT17 VCT16
R/W R R R
Initial value X X X
Bit 15 14 13
Name VCT15 VCT14 VCT13 VCT12 VCT11 VCT10 VCT9
R/W R R R
Initial value X X X
Bit field
Number Name
31-0 VCT31-0
After the IRQF bit of the RQF register is set to "1", the displayed vector address value is not changed
until the IRQF bit is cleared. The interrupt level is decided again after the IRQF bit is cleared, and the
display is updated by the source that sets the IRQF bit. When "1" is not set to the IRQF bit, the
register value is not defined.
The firmware diverges to the address specified for the VCT register (It is divergent to the expansion
vector table) by the instruction put on IRQ vector (0000_0018
the instruction continuously put in the address. It can know whether a new IRQ source is higher than
a current interrupt among interrupt handlers when the IRQF bit is cleared once after it diverges to the
interrupt handler by the assert of IRQ.
9-22
IRC0:
or FFFE_8000 + 20
H H H
28 27 26 25
R R R R
X X X X
12 11 10 9
R R R R
X X X X
Display the interrupt vector table to the interrupt source that should be processed.
The displayed vector value is a value that the offset value of each interrupt factor was added to
the upper address value set depending on the TBR register.
Table 9-2 Expansion IRQ interrupt vectors of IRC0
Refer to "
Expansion IRQ interrupt vector of IRC1
the interrupt level register, and the vector address.
The initial value of these bits is undefined.
IRC1: FFFB_0000
IRC2: FFFB_1000
24 23 22 21
R R R R
X X X X
8 7 6 5
VCT8 VCT7 VCT6 VCT5
R R R R
X X X X
Explanation
" for the relation among the interrupt source,
). It diverges to the interrupt handler by
H
+ 20
H H
+ 20
H H
20 19 18 17
R R R R
X X X X
4 3 2 1
VCT4 VCT3 VCT2 VCT1
R R R R
X X X X
Table 9-3
" and "
16
R
X
0
VCT0
R
X