I2Sxrxfdat Register - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

27.6.3 I2SxRXFDAT register

This register is reception FIFO register that is able to maintain up to 66 words (simultaneous
transfer mode) or 132 words (reception only mode.)
Address
Bit 31 30 29
Name
R/W R R R
Initial 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial 0 0 0
Bit field
No. Name
31-0 RXDATA[31:0] The word received from serial bus is written to reception FIFO.
27-6
ch0：FFEE_0000 (h)
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
R R R R
0 0 0 0
When frame is 1 sub frame construction and word length set to S0WDLN of MCR0REG
register is 32 bit or less (16 bit when RHLL of CNTREG register is "1"), it is written to
reception FIFO after higher order bit is extended.
When frame is 2 sub frame construction and word length set to S0WDLN of MCR0REG
register is 32 bit or less (16 bit when RHLL of CNTREG register is "1"), reception data of
sub frame 0 is written to reception FIFO after higher order bit is extended.
For the case that word length set to S1WDL of MCR0REG register is 32 bit or less,
reception data of sub frame 1 is written to reception FIFO after higher order bit is
extended.
When BEXT of CNTREG register is "1", it is extended with MSB of reception word (sign
extension). For the case that the value is "0", it is enhanced by "0".
Top of the data (First In) of reception FIFO is able to be read by read access, and then
the next reception FIFO data is automatically updated. It is able to be accessed
regardless of shift register's operation status. When RXNUM of STATUS register is
"0", invalid data is able to be read. Writing to RXDATA is ignored.
24 23 22 21
RXDATA
R R R R
0 0 0 0
8 7 6 5
RXDATA
R R R R
0 0 0 0
Description
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
R R R R
0 0 0 0
16
R
0
0
R
0