Expansion Cs Register (I2Cxecsr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

29.7.8 Expansion CS register (I2CxECSR)

Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial
valu 0 0 0
e
Bit 5-0: CS10-5 (Clock Period Select 10-5)
This is set to expand the upper limit of the bus clock frequency by extending CS4 ~ 0 in the
I2CxCCR register.
The initial value of CS10 ~ 5 is "000000" and setting other values enters the frequency upper limit
expansion mode.
CS10~5
000000
Other than 000000
29-18
ch0：FFF5_6000 + 14h ch1：FFF5_7000 + 14h
28 27 26 25 24
R R R R
0 0 0 0
12 11 10 9
(Reserved)
R R R R
0 0 0 0
No upper limit expansion of the bus clock frequency
(only CS4 ~ 0 is used)
Upper limit expansion of the bus clock frequency
23 22 21 20
(Reserved)
R R R R
0 0 0 0
8 7 6 5
(Reserved)
R R R R/W R/W R/W R/W R/W R/W
0 0 0 0
State
19 18 17 16
R R R R
0 0 0 0
4 3 2 1
CS[10:5]
0 0 0 0
R
0
0
0