Two Bus Control Registers (I2Cxbc2R) - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

29.7.7 Two bus control registers (I2CxBC2R)

Address
Bit
31
30
29
Name
R/W
R
R
R
Initial value
0
0
0
Bit
15
14
13
Name
R/W
R
R
R
Initial
valu
0
0
0
e
Bit 7 and 6: Unused
The value is always "00" on reads.
Bit 5: SDAS (SDA status)
Indicates the signal level of the SDA line after passing the noise filter.
Only reading is valid.
SDAS
0
The SDA line is "0"
1
The SDA line is "1"
Bit 4: SCLS (SCL status)
Indicates the signal level of the SCL line after passing the noise filter.
Only reading is valid.
SCLS
0
SCL line is "0"
1
SCL line is "1"
Bit 3 and 2: Unused
The value is always "00" on reads.
Bit 1: SDAL (SDA low drive)
The SDAO output is forced to "L".
Both reading/writing are valid.
SDAL
0
SDAO output is in normal operation
1
SDAO output is forced to "L"
Bit 0: SCLL (SCL Low drive)
The SCLO output is forced to "L".
Both reading/writing are valid.
SCLL
0
SCLO output is in normal operation
1
SCLO output is forced to "L"
ch0:FFF5_6000 + 1Ch ch1:FFF5_7000 + 1Ch
28
27
26
25
R
R
R
R
0
0
0
0
12
11
10
9
(Reserved)
R
R
R
R
0
0
0
0
24
23
22
21
(Reserved)
R
R
R
R
0
0
0
0
8
7
6
5
(Reserved)
SDAS SCLS
R
R
R
R
0
X
State
State
State
State
20
19
18
17
R
R
R
R
0
0
0
0
4
3
2
1
(Reserved)
SDAL SCLL
R
R
R
R/W R/W
X
0
29-17
16
R
0
0
0

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