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MB86R02 'Jade-D' Hardware Manual V1.64
8.6
Operation
This section describes the RBC's operation.
8.6.1
RBC reset
The RBC has two reset input ports.
The RBREMAP register is reset by the HRESETn input and RBVIHA and RBITRA registers are
reset by the CRSTn value.
Table 8-3 shows the correlation between these resets and registers.
Table 8-3 Correlation between reset and register
Reset input
HRESETn
RBREMAP
CRSTn
RBVIHA
RBITRA
8.6.2
Remap control
A remap changes the vector area (00000000
The vector area is allocated to the built-in boot ROM at power-on and the system starts from it.
Using the remap control, the allocated area is changed to the built-in SRAM_1 memory allowing
the built-in vector table to be effectively overwritten.
8.6.3
VINITHI control
The ARM926EJ-S core has a VINITHI signal which determines the exception vector address.
When low at reset, the exception vector is located at 00000000
the exception vector is located in FFFF0000
Refer to the "Technical reference manual" of ARM9 provided by ARM Ltd. for details about the
VINITHI signal.
The initial value of the RBVIHA register is defined by the external pin, VINITHI.
Limitation:
If VINITHI is high, then exception vectors have to be stored at physical address (00000000
00008000
). It is not possible to simultaneously use this with a remapped vector area to
H
SRAM_1. (VINITHI =1 in conjunction with REMAP=1 is not allowed)
Register
This port is reset by HRESETn.
This port value reflects to value of external pin, VINITHI by CRSTn.
input.
This port is reset by CRSTn input.
H
Description
～00008000
) after power-on.
H
H
. When the signal is high at reset,
H
.
～
H
8-7
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