Basic Transmission Operation - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

28.7.4 Basic transmission operation

M ar k st at e

When initial reset is completed and transmission data is not written to the Transmission shift

transmission (SOUT) pin. The data is output from serial transmission (SOUT) pin with adding

start bit, parity bit, and stop bit in the transmission control part as shown in Figure 28-5 when

transmission data is written from CPU to transmission FIFO.

1 ~ 16 byte of transmission data is able to be consecutively written to transmission FIFO at a time.

Transmission FIFO state is able to be confirmed with THRE bit of the LSR register.

When transmission data is written to transmission FIFO though it is full, the last written data is

deleted. The data that is already stored in the transmission FIFO is properly transmitted.

THRE bit becomes "0" by writing to transmission FIFO. When the writing data is transferred to

the Transmission shift register and FIFO becomes empty, the value becomes "1". If

transmission data buffer interrupt is permitted in that time, interrupt (INTR) pin becomes "H" and

interrupt occurs. This interrupt is released by writing data to the transmission FIFO again or

reading the Interrupt confirmation register.

TEMT bit becomes "0" at the same timing of THRE bit, and the value becomes "1" after

transmission of all written data is completed.

XTXRDY is data ready signal that shows possible transmission to DMA controller at using the

controller. Single transfer mode is supported when bit 3 of the FCR register is "0" and the

demand transfer mode is supported when the bit is "1". Note: Please use Demand mode to

transfer data from/to the UART. This allows continous operation, even if the UART fill level is

higher than the DMA transfer size.

When transmission baud rate used by macro is within the reception baud rate permissible error

range, the other party is able to receive data. Out of the range causes reception error on the

other party side.

1 char act er

Thi s i s exam pl e of t he case, dat a bi t l engt h i s 6 bi t and st op bi t l engt h i s 2 bi t , and par i t y

Figure 28-5 Basic transmission operation

Par i t y bi t