Address Register (I2Cxadr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

29.7.5 Address register (I2CxADR)

Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial
valu 0 0 0
e
Bit 7: Unused
The value is always read as '1'.
Bit 6-0: A6-0 (Address 6-0)
This is the slave address storage bit.
The comparison with the I2CxDAR register is performed after address data reception at the slave.
If they are matched, an acknowledge is transmitted to the master.
ch0：FFF5_6000 + 0Ch ch1：FFF5_7000 + 0Ch
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
(Reserved)
R R R R
0 0 0 0
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
(Reserved)
R R R/W R/W R/W R/W R/W R/W R/W
0 1 X X
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
A[6:0]
X X X X
29-15
16
R
0
0
X