Transfer Start, Stop, And Malfunction - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

27.7.2 Transfer start, stop, and malfunction

Transmission only mode
Transfer Operation
setting
Transmissio Start
n
only
TXDIS = 0
RXDIS = 1
Stop At the time of stop, transmission FIFO
Master mode (MSMD = 1)
Free-running mode (FRUN = 1):
After start bit becomes "1" and TXENB bit
is "1", frame synchronous signal starts to
output when transmission FIFO is not
empty. From the 2nd time, it outputs
frame synchronous signal with the frame
rate determined by the register setting. If
transfer FIFO is empty, empty frame is
output at the same time of frame
synchronous signal output.
Serial data of the empty frame is able to be
set to "0" or "1" by the register setting.
Burst mode (FRUN = 0):
When start bit is "1" and TXENB bit is "1",
frame synchronous signal is output if
transfer FIFO is not empty. Always
confirm transmission FIFO status at the
end of 1 frame output or at idle to output the
signal if transfer FIFO is not empty.
becomes empty with having no data
transfer from internal memory to I2S
transmission FIFO.
To maintain start bit to "1"
TXENB = "1":
Keep outputting frame synchronous signal
in the free-running mode. When
transmission FIFO becomes empty, empty
frame is output; however do not output
frame synchronous signal in the burst
mode. Output empty frame bit to serial
data bus.
TXENB = "0":
When "0" is written to TXENB, transmission
FIFO becomes empty that the data in the
FIFO at writing "0" is not sent.
Although frame synchronous signal
continues outputting in the free-running
mode, serial bus becomes in high
impedance state. In the burst mode,
frame synchronous signal is not output and
serial data bus becomes in high impedance
state.
To make start bit "0"
Write "0" to start bit, then transmission
FIFO becomes empty. Stop clock supply
to the serial control part regardless of
TXENB setting, and do not output clock to
external part. Frame synchronous signal
output should also be stopped.
Serial data bus becomes in high
impedance state.
Slave mode (MSMD = 0)
Free-running mode (FRUN = 1):
The frame rate determined by the register
setting inputs frame synchronous signal.
If transmission FIFO is empty at inputting
frame synchronous signal with start bit is
"1" and TXENB bit is "1", empty frame is
output.
Serial data of the empty frame is able to be
set to "0" or "1" by the register setting.
Burst mode (FRUN=0):
When start bit is "1" and TXENB bit is "1", 1
frame is output every time frame
synchronous signal is input. When
transmission FIFO is empty at the time of
frame synchronous signal input, empty
frame is output.
To maintain start bit to "1"
TXENB = "1":
Output empty frame data to serial
bus.
TXENB = "0":
Write "0" to TXENB, then transmission
FIFO becomes empty that the data in the
FIFO at writing "0" is not sent. Data
writing to transmission FIFO and
transmission frame detection are stop.
Serial data bus becomes in high
impedance state.
To make start bit "0"
Write "0" to start bit, then transmission
FIFO becomes empty.
Writing to transmission FIFO and detection
of transmission frame synchronous signal
are stop regardless of TXENB setting.
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