Dram Ctrl Fifo Register (Drcf) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
13.6.10

DRAM CTRL FIFO register (DRCF)

This is DDR2C's internal FIFO control related register.
Address
Bit 15 14 13
Name *1 - -
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 X X
*1: FIFO_ARB
Bit field
No. Name
15 FIFO_ARB
14-5 (Reserved)
4-0 FIFO_CNT
12 11 10 9
- - - -
X X X X
Capture bandwidth is improved.
0 Default
1 Capture bandwidth is improved.
Reserved bits.
Write access is ignored.
FIFO FULL count.
This is number of stage setting of address FIFO (FULL condition.)
When picture flickers due to AXI access latency at using display and capture, it is
recovered by reducing number of FIFO stage and decreasing AXI bus latency.
Bit[4:0] Address FIFO number of
stage
00 - 01
H H
02
H
03
H
04
H
05
H
06
H
07
H
08
H
09
H
0A
H
0B
H
0C
H
0D
H
0E
H
0F
H
10
H
11
H
12
H
13
H
14
H
15
H
16
H
17 - 1F
H H
F300_0000 + 20
H H
8 7 6 5
- - - -
X X X X
Description
- Reserved (setting
prohibited)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 (Initial value)
- Reserved (setting
prohibited)
4 3 2 1
FIFO_CNT
R/W
1 0 1 1
13-15
0
0