Modem Control Register (Urtxmcr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

28.6.8 Modem control register (URTxMCR)

ch0：FFFE_1000 + 10h ch1：FFFE_2000 + 10h ch2：FFF5_0000 + 10h
Address
ch3：FFF5_1000 + 10h ch4：FFF4_3000 + 10h ch5：FFF4_4000 + 10h
Bit 31 30 29
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
valu X X X
e
Bit No. Bit name
31:8 Unused
7:5 Unused
4 LOOP
3 OUT2
2 OUT1
1 RTS
0 DTR
* Bit7:0 = 00h, after reset
28 27 26 25
X X X X
12 11 10 9
(Reserved)
X X X X
Reserved bit (input "0" at writing)
Reserved bit (input "0" at writing)
Loop Back Mode (self-diagnostic mode)
When loop is set to "1", following is performed.
1. SOUT becomes "1"
2. SIN is separated from input Shift register of reception
3. Transmission shift register output is connected to input of the Reception shift
register
4. Modem status is separated (NCTS, NDSR, NDCD, and NRI)
5. Modem control signal is connected to modem status input
CTS – RTS
DSR – DTR
RI – OUT1
DCD – OUT2
Control signal
"1" makes output pin active.
24 23 22 21
(Reserved)
X X X X
8 7 6 5
(Reserved) LOOP OUT2 OUT1
X 0 0 0
Function
20 19 18 17
X X X X
4 3 2 1
RTS DTR
0 0 0 0
28-11
16
X
0
0