External Interfaces; Communication Protocols (Timing Diagrams); Spi Protocol Stack - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
16.4.

External Interfaces

16.4.1. Communication Protocols (Timing Diagrams)

16.4.1.1.

SPI protocol stack

The SPI communication protocol stack is shown below.
CPU BUS
Modules
(RxRDY TxRDY)
interrupt
Controller
Host CPU
BUS
DATA
Handshaking
RST
SPI
interrupt
Figure 16-8 SPI communication protocol stack
AHB Master
Handshaking
(RxRDY TxRDY)
SPI interface
AHB Modules
DATA
RST
CCNT
SPI
CCNT
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