Fujitsu MB86R02 Jade-D Hardware Manual page 280

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MB86R02 'Jade-D' Hardware Manual V1.64

Restrictions

When DMA transfer is performed by an external (DREQ) or peripheral (IDREQ) request, there

are restrictions for external and peripheral signal pins.

1. DREQ/IDREQ

DREQ/IDREQ must be asserted for at least 2 cycles of the AHB clock (HCLK).

There is no restriction for the timing of negating DREQ/IDREQ.

After asserting DACK/IDACK, DMAC is able to accept new a transfer request (edge of

DREQ/IDREQ) for the next DMA transfer.

2. DACK/IDACK

After the DMAC transfers data to the destination address, DACK/IDACK are asserted for 1

cycle of the AHB clock (HCLK). If access to the destination is executed correctly, this signal

is asserted. If destination issues, error, retry or split responses occur on the AHB, it is not

In block transfer mode, these signals indicate that the DMAC has correctly performed

destination access.

3. DEOP (Data End Operation)/IDEOP

Basically, DEOP/IDEOP is asserted for 1 AHB clock (HCLK) cycle if the DMAC terminates

DMA transfer properly or abnormally. Abnormal DMA transfer includes the following cases:

• Forced termination by DSTP/IDSTP

• Forced termination by setting 1'b0 to DMACA/EB

• Reception of an error response from the source/destination

4. DSTP (Data Stop)/IDSTP

DSTP/IDSTP are used to forcibly terminate DMA transfer and asserting them during the

transfer is permitted (it is also permissible to assert DSTP/IDSTP while DMA data is not

transferred due to a transfer gap or an interrupt function).

If these signals are used to forcibly terminate DMA transfer, they are not asserted until

DEOP/IDEOP are asserted.

5. Exceptional operation of DEOP/IDEOP

If DSTP/IDSTP are asserted immediately after asserting DREQ/DSTP, the DMAC may

request the bus to execute an IDLE transfer. In this case, the DMAC may assert

DEOP/IDEOP for 2 or more cycles of the AHB clock (HCLK).

The assertion period of DEOP/IDEOP depends on the number of previous master transfer

cycles. Figure 15-2 shows an example of this exception operation.