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MB86R02 'Jade-D' Hardware Manual V1.64
L5ETC (L5 layer Extend Transparency Control)
Register
DisplayBaseAddress + 0x1B4
address
Bit number
31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
L5ETZ
R/W
RW
Initial value
0
This register sets the transparent color for the L5 layer. This register sets the transparent color for
the L5 layer. When L5ETC = 0 and L5EZT = 0, color 0 is displayed in black (transparent).
Bit 23 to 0
L5ETC (L5 layer Extend Transparent Color)
Sets transparent color code for the L5 layer. In indirect color mode (8 bits/pixel) bits 7 to 0
are used.
Bit 31
L5EZT (L5 layer Extend Zero Transparency)
Sets handling of color code 0 in L5 layer
0
Code 0 as transparency color
1
Code 0 as non-transparency color
Reserved
R0
0
L5TEC
RW
18-113
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