Registers; Register List - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
26.9

Registers

This section describes the A/D converter registers.
26.9.1

Register list

This LSI has 2 ADC instances controlling 4 channels. The registers shown below in Table 15-1
control the ADC functionality of the device.
Table 26-1 Register Summary
Address
Channel
Base Offset
ADC 0 FFF5_2000 + 00
H
+ 04
+ 08
+ 0C
+ 10
+ 14
ADC 1 FFF5_3000 + 00
H
+ 04
+ 08
+ 0C
+ 10
+ 14
Note:
Access all ADC channel areas using 32 bit (word) accesses.
Register
ADC 0 data register
H
ADC0 mode register
H
ADC 0 power down
H
control register
(Reserved)
H
ADC 0 clock selection
H
register
ADC 0 status register
H
ADC 1 data register
H
ADC1 mode register
H
Down of ADC 1 power
H
control register
(Reserved)
H
ADC 1 clock selection
H
register
ADC 1 status register
H
Abbreviation Description
ADC0DATA A/D converted data is stored
ADC0MODE Sampling mode is set
ADC0XPD Power down mode is set/released
– Reserved area, access prohibited
ADC0CKSEL Clock frequency is supplied to A/D
converter
ADC0STATUS A/D converted data is stored to data
register
ADC1DATA A/D converted data is stored
ADC1MODE Sampling mode is set
ADC1XPD Power down mode is set/released
– Reserved area, access prohibited
ADC1CKSEL Clock frequency is supplied to A/D
converter
ADC1STATUS A/D converted data is stored to data
register
26-5