Fujitsu MB86R02 Jade-D Hardware Manual page 327

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MB86R02 'Jade-D' Hardware Manual V1.64
Register address
BaseAddress + 74
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Field name
Reserved
R/W
RWS
Reset value
Channel 1 RX 0 control
Bit
Reserved
31 -
Do not modify
24
Bit 2
R1CFGEN
0: A-Shell and PHY running (write protection on APCFG registers), with falling edge config registers ore overtaken by PHY. 1: (def) A-
Shell and PHY configuration (possible to change APCFG registers), Ashell and PHY (if EnRstToPhy is enabled) is hold in reset, Changes
at configurations bytes (config_byte_*) are allowed only when 'CFGEN' or 'RSTRT' are asserted.
Bit 1
Reserved
Do not modify
R1STS0
Register address
BaseAddress + 78
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18
R/W
Reset value
Channel 1 RX status register 0
Bit 31
Reserved
- 24
Do not modify
Bit 17
Reserved
Do not modify
Bit 10
R1PXALIGND
rx_pix_aligned, 1=Pixel link operational
Bit 9
Reserved
Do not modify
Bit 8
Reserved
Do not modify
Bit 7
Reserved
Do not modify
Bit 6
Reserved
Do not modify
Bit 5
Reserved
Do not modify
Bit 4
Reserved
Do not modify
Bit 3
Reserved
Do not modify
Bit 2
Reserved
Do not modify
Bit 1
R1PHYDWNRDY
indicates that downstream serial channel (APIX PHY) is operational, While 'PHYDWNRDY' is low AShell can't become TA aligned
('CONNECTED' is low). If the local APIX PHY is not used 'PHYDWNRDY' is forced to '1' (rx_down_ready).
Bit 0
R1PLLGOOD
pll_good (is the same for all Tx/Rx channels)
R1STS1
Register address
BaseAddress + 7C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Channel 1 RX status register 1
Bit 31 - 24
Reserved
Do not modify
Bit 20 - 16
R1Eye
Measured eye opening, 1=edge in this phase during measurement period was set by Eyetime
Bit 15 - 8
R1INSYNC
Synchronisation losses rx_down__sync_loss_cnt
Bit 7 - 0
R1PLLBAD
17-14
H
0
H
H
RWS
0
H
H
Reserved
R
0
H
17
16 15 14 13 12 11 10 9
R
R
R
0
0
0
H
H
H
R1Eye
R1INSYNC
R
X
2
1
R1CFGEN
Reserved
RW
RW
1
0
H
H
8
7
6
5
4
3
2
1
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
H
H
H
H
H
H
H
H
R1PLLBAD
R
R
0
0
H
H
0
0
R
0
H

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