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MB86R02 'Jade-D' Hardware Manual V1.64
PLL Control
Oscillation stabilization waiting period
The clock transmission source for the oscillation stabilization waiting period is the count
value of the time-based timer. Clearing the time-based timer effects its count value. If this
module's state is changed to PLL oscillation stabilization waiting state as shown below, the
time-based timer is cleared.
(1) External reset is asserted ("M" and "m" of LUWMODE in the 5.1.2 PLL control
register (CRPR))
6 CLK cycles
XRST
ERSTn
PLL reset
CLK
1/M PLL clock
CCLK
HRESETn
PLLREADY
PLLBYPASS
Figure 5-8 PLL oscillation stabilization waiting state after external reset
2
(m
+ 2) CLK
cycles
a)
b)
c)
a)
b)
c)
d)
e)
PLL oscillation
stabilization waiting
d)
External reset deasserted (XRST)
ERSTn reset (CRG internal signal)
PLL reset deasserted
PLL ready
HRESETn deasserted
21 or more CCLK cycles
e)
5-11
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