Ahb (A) Bus Clock Gate Control Register (Crha) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
5.1.7.

AHB (A) bus clock gate control register (CRHA)

This register controls clock gate of AHB (A) bus.
Address
Bit 31 30 29
Name – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1
Bit field
No. Name
–
31-24
23-0 HAGATE[23:0] HACLK clock gate control
5-28
28 27 26 25
– – – –
X X X X
12 11 10 9
1 1 1 1
Unused bits.
Write access is ignored, and read value of these bits is undefined.
These bits control HACLK clock gate.
HAGATE[n]
0 HACLKn stops
1 HACLKn does not stop (initial value)
HACLK0: AHB1, AHB2, APBBRG0, APBBRG1, APBBRG2, AHB2AHB
HACLK1: External bus I/F, CCPB
HACLK2: SRAM
HACLK3: HDMAC
HACLK4: (Reserved)
HACLK5: Boot ROM
HACLK6: (Reserved)
HACLK7: I2S
HACLK8: (Reserved)
HACLK9: (Reserved)
HACLK10: SD I/F
HACLK11: (Reserved)
HACLK12: MLB
HACLK13: GDC
HACLK14: (Reserved)
HACLK15: DDR2 controller
HACLK16: RH TX0
HACLK17: RH TX1
HACLK18: RH RX0
HACLK19: RH RX1
HACLK20: RLD
HACLK21: DPERI0
HACLK22: DPERI1
HACLK23: SPI-HOST
FFFE_7000 + 18
H H
24 23 22 21
–
X 1 1 1
8 7 6 5
HAGATE[15:0]
1 1 1 1
Description
Description
20 19 18 17
HAGATE[23:16]
1 1 1 1
4 3 2 1
1 1 1 1
16
1
0
1