Fujitsu MB86R02 Jade-D Hardware Manual page 291

MB86R02 'Jade-D' Hardware Manual V1.64
Timing chart
Figure 15-7 shows a demand transfer timing chart.
External trigger
DREQ
DACK
DEOP
DSTP
HBUSREQ
HGRANT
HCLK
CPU
HMASTER
HTRANS
HADDR
HWRITE
Control
HWDATA
HRDATA
HREADY
HRESP
DMACA[19:16]
BC
DMACA[15:0] 0x0
TC
Figure 15-7 Demand transfer (for BC = 0x0 (should be 0) and TC = 0x2)
15-28
Transfer gap
HDMAC CPU HDMAC
N N N N
I
DA
SA SA
Data
Data
OK
0x2
0x1
Transfer gap
I
DA
Data
Data
HDMAC
N N I
DA
SA
Data
Data
0x0
0x0