Dma Configuration A Register (Dmacax) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

15.6.3 DMA configuration A register (DMACAx)

ch0：FFFD_0000+10 (h) ch1：FFFD_0000+20 (h) ch2：FFFD_0000+30 (h)
Address
ch4：FFFD_0000+50 (h) ch5：FFFD_0000+60 (h) ch6：FFFD_0000+70 (h)
Bit 31 30 29
Name EB PB ST
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit field
No. Name
31 EB This bit is used to control DMA channel transfer.
(Enable Bit) When "1" is set to this bit, channel waits for the trigger to start DMA transfer (DMACR/DE
bits should be set to "1" beforehand.)
DMAC sets "0" to this bit after DMA transfer, then this channel is disabled and DMA
transfer is not performed until "1" is set to this bit. If "0" is set to this bit during DMA
transfer, DMA stops at transfer gap which is regarded as forcible termination.
Refer to DMACR/DE bits description for transfer gap.
This bit is able to use for resetting each configuration register of the channel during DMA
transfer.
30 PB This bit is used to discontinue DMA channel transfer.
(Pause Bit) When "1" is set to this bit, this channel stops the transfer, and it is not performed until this
bit is cleared.
If "1" is set to this bit during DMA transfer, DMA stops at transfer gap. Refer to
DMACR/DE bits description for transfer gap.
When "1" is set to this bit before receiving transfer request to acquire bus right, DMAC is
immediately paused; in this case, DMAC does not hold transfer request during the
pause.
When "0" is set to this bit during DMA transfer is in pause, it is cleared and DMAC waits
for new transfer request.
This bit is able to be used to stop DMA transfer without resetting each configuration
register of the channel.
15-8
28 27 26 25
IS[4:0]
0 0 0 0
12 11 10 9
0 0 0 0
0 This channel is disabled (initial value)
1 This channel is enabled
0 Initial value
1 This channel is stopped
FFFD_0000+40 (h)
FFFD_0000+80 (h)
24 23 22 21
BT[3:0]
0 0 0 0
8 7 6 5
TC[15:0]
0 0 0 0
Description
ch3：
ch7：
20 19 18 17
BC[3:0]
0 0 0 0
4 3 2 1
0 0 0 0
16
0
0
0