Block Functions - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

29.4 Block functions

The function of each block is described below.
Block
Start condition/Stop
condition detector
Start condition/Stop
condition generator
Arbitration lost detector
Shift clock generator
Comparator
I2CxADR
I2CxDAR
I2CxBSR
I2CxBCR
I2CxCCR
Noise filter
I2CxBC2R
I2CxECSR
I2CxBCFR
Start condition and Stop condition are detected by the transition
state of the SDA and SCL lines.
The Start condition and Stop condition are generated by the
transition state of the SDA and SCL lines.
Output data to SDA line and input data from SDA line are compared
at data transmission.
If they do not match, arbitration is lost.
Timing count of serial data t transfer clock occurrence and output
control of SCL line clock are performed via the clock control register
setting.
Compares the received address and self-address specified in the
address register or received address and global address.
7 bit register that specifies the slave address.
8 bit register used for serial data transfer.
8 bit register with following functions to show I
others.
•
Repeated start condition detection
•
Arbitration lost detection
•
Acknowledge bit storage
•
Direction of data transfer
•
Addressing detection
•
General call address detection
•
First byte detection
8 bit register that performs I
following functions.
•
Interrupt request/permission
•
Start condition occurrence
•
Master/Slave selection
•
Acknowledge occurrence permission
7 bit register that sets clock frequency of serial data transfer.
•
Operation permission
•
Frequency setting of serial clock
•
Standard/High-speed mode selection
This noise filter is composed of a 3-stage shift register circuit.
If all 3 values consecutively sampled on the SCL/SDA lines are "1",
the filter output is a "1". If the values are all "0", the filter output is "0".
For other sampled values, the previous state 1 clock is maintained.
This is the register to drive "L" forcibly and to confirm the line status
after the noise filter.
This is the register to enhance CS bit in I2CxCCR register.
This is the register that specifies the frequency range of the bus
clock to be used.
Description
2
C bus status and
2
C bus control and interrupt control has
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