MB86R02 'Jade-D' Hardware Manual V1.64
34.5.2.1
DDR2SDRAM Interface Timing Diagram
MB86R01
DDR2 SDRAM (DDR2-400)
CK
DDR2C
CMD/AD
DQ
DQS
Timing regulation point
* External load condition: PCB design guideline
Figure 34-13 Timing Regulation Point
34-21
