Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
Bit
init
Name
ial
cfg_sbdown_daclk
7
0
Reserved, cfg_ephy
6
0
Reserved,
5
0
cfg_mode_sb
4
0
cfg_crc_timeout_value [3]
3
1
cfg_crc_timeout_value [2]
2
0
cfg_crc_timeout_value [1]
1
0
cfg_crc_timeout_value [0]
0
1
Table 17-13 RX config_byte_shell3
17-24
config_byte_shell3
cfg_eshell
Description
AShell:
validate sbdown_data with
1: sbdown_data[1],
0: internal signal (sbdown_valid)
AShell: connect internal AShell to
external APIX
PHY (INAP125R24) through GPIO
interface
1: enable
0: disable
AShell: connect internal APIX PHY to
external
Ashell through GPIO interface. To use this
mode 'cfg_ephy' enable is required.
1: enable
0: disable
AShell: selects between two different
sideband
transmission modes
0: mode 0 (toggle mode), see
1: mode 1, see
Figure 17-29
AShell: CRC timeout error is generated
after N consecutively received and
corrupted transitions (CRC mismatch)
N = factor1 * factor2
factor1 = cfg_crc_timeout_value [3:2]
factor2 = cfg_crc_timeout_value [1:0]
factor 1
factor 2
00: 1
00: 2
01: 4
01: 4
10: 16
11: 128
11: 10
example: 1001 N = 64 (16*4)
Note: to achieve optimum system
behaviour, please adapt to bit fault
characteristics of serial link
,
Figure 17-28
10: 6
Advertisement
Table of Contents
