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MB86R02 'Jade-D' Hardware Manual V1.64
7.4.15 MBUS2AXU set register (CMBUS)
Address
Bit
31
30
29
Name
(Reserved)
R/W
R
R
R
Initial value 0
0
0
Bit
15
14
13
Name
(Reserved)
R/W
R
R
R
Initial value 0
0
0
Bit field
Number
Name
31-5
(Reserved)
DRAW_MBUS_WTWAIT
4
DRAW_MBUS_RTWAIT
3
DRAW_MBUS_FCAP
2-0
7-24
FFF4_2000 + 44h
28
27
26
25
R
R
R
R
0
0
0
0
12
11
10
9
R
R
R
R
0
0
0
0
Reserved
Writes are ignored. Reads will return a '0' at all times.
Transaction wait setting for write transaction The next transaction is not begun until the
transaction is completed on an internal bus.
0
Don't wait
1
Wait
Transaction wait setting for read transaction The next transaction is not begun until the
transaction is completed on an internal bus.
0
Don't wait
1
Wait
Built-in FIFO steps number setting.
8 steps
000
1 step
001
2 steps
010
3 steps
011
100
4 steps
5 steps
101
110
6 steps
111
7 steps
24
23
22
21
R
R
R
R
0
0
0
0
8
7
6
5
R
R
R
R
0
0
0
0
Function
20
19
18
17
R
R
R
R
0
0
0
0
4
3
2
1
WTWAIT
RTWAIT
FCAP[2:0]
R/W
R/W
R/W
R/W
0
0
0
0
16
R
0
0
R/W
0
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