Fujitsu MB86R02 Jade-D Hardware Manual page 221

MB86R02 'Jade-D' Hardware Manual V1.64
Read/Write to low-speed device
Internal clock
MEM_EA[24:1]
X
MEM_ED[15:0]
MEM_XRD
MEM_XWR[1:0]
MEM_XCS[4/2/0]
MEM_RDY
tRADC= Read address setup cycle
tRACC= Read access cycle
tRIDLC= Read idle cycle
Figure 11-2 Half word read access to 16 bit width low speed device
Internal clock
MEM_EA[24:1]
X
1 cycle
MEM_ED[15:0]
MEM_XRD
MEM_XWR[1:0]
MEM_XCS[4/2/0]
MEM_RDY
tWADC = Write address setup cycle
tWACC = Write access cycle
tWWEC = Write enable cycle
tWIDLC = Write idle cycle
Figure 11-3 Half word write access to 16 bit width low speed device
11-14
00
tRADC
tRACC + Wait cycle
Wait cycle
Min 2 cycles
00
X
tWADC
tWACC + Wait cycle
Wait cycle
Min 2 cycles
D00
tRIDLC
1 cycle
D00
tWIDLC
tWWEC
X
X